Semiconductor devices include metal layers that are insulated from each other by dielectric layers. As device features shrink, reducing the distance between the metal lines on each layer, capacitance increases. The parasitic capacitance may contribute to effects such as RC delay, power dissipation, and capacitively coupled signals, also known as cross-talk. To address this problem, insulating materials that have relatively low dielectric constants (referred to as low-k dielectrics) are being used in place of silicon dioxide (and other materials that have relatively high dielectric constants) to form the dielectric layer that separates the metal lines.
One way to lower the dielectric constant is to form pores in the dielectric material. For example, some dielectric materials use thermally activated porogens. When heat is applied, the porogen may decompose and/or volatilize, leaving pores in the dielectric material. For example, temperatures in the range of about 250 degrees C. to about 450 degrees C., which may be reached in dual damascene processing, may be used to thermally activate a porogen.
Lower dielectric constants are possible because the pores are voids having dielectric constants near one (1). However, porous dielectric materials have several problems that make those materials difficult to integrate into normal semiconductor processing such as dual damascene processes.
Problems with dielectric materials having thermally activated porogens include surface roughness after etching, non-continuous metal barrier coverage, rough metal barrier interfaces, and susceptibility to chemical decomposition or k-value degradation during dry etch and wet clean processes. Surface roughness and poor barrier coverage may result in significant resistivity variation, uncontrolled copper diffusion, and reduced device reliability.
Surface roughness due to porosity of the dielectric material is a problem because metal interconnects need smooth side walls to maintain low resistance. Surface roughness can significantly increase the resistance of interconnects for integrated circuit devices dimensioned lower than 100 nanometers. For theses reasons, integrating a porous dielectric layer in integrated circuit manufacturing is a problem, especially in dual damascene processes.
What is needed is a dielectric material that may be made porous without the problems of surface roughness and poor barrier coverage. A method of providing a porous dielectric material having a low dielectric constant is needed for increasingly smaller semiconductor device geometries.